LAT  Electronics, Data Acquisition & Instrument Flight Software

  Subsystem Manager:  Gunther Haller

 

Important: EM2 test-stand hardware components are NOT compatible with hardware supplied for EM1 test-stands. Do not mix TEM/TEM-PS/Transition Card EM1 with EM2 hardware. Hardware for EM2 is marked "EM2" on the TEM, TEM-PS, VME Transition Card and LCB supplied.

Documents:

The documents are in the process of being transferred to the LAT-DOC system for official release, please retrieve them from LATDOC's.

Here are applicable document numbers and selected copies of the documents in the release cycle (use them with caution).

Note that we do not perform impedance/short/open/voltage measurements on all pins, but test functionality of the system. The "safe-to-mate" test is the responsibility of the sub-system.

Tracker:

EGSE-TKR TESTSTAND #4

LAT Quality Assurance

Performance & Safety Assurance LAT NCR Report

The following Nonconformance Report # 00155 was submitted on 08/30/04 16:04:59

 

Entered by Ludvik, Jeffrey - jsludvik@slac.stanford.edu

 

Found by:  Customer Complaint

Type of Nonconformance:  Minor

Discrepancy Level:  Non-Flight Hardware

Sub-System:  Electronics (ELEC)

Item Description:  EGSE TKR Teststand #4

Supplier: 

Location: 

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Test Procedure/Rev #: 

 
Description of Nonconformance:  INFN described the problem as: "The baseline voltages on the RESET LVDS loop were higher than the normal value (RESET_P = 3.16 V, RESET_M = 3.12 V, should be ~ 1.2 V). We used to get strip numbers out of range (i.e. > 1535) when reading out data" TEM/TPS modules of TKR Teststand #4 were returned to SLAC for repair. Upon return TEM failed normal test procedure. On connector JT6, a GTCC1 ASIC, U55, the test software failed. It is possible the ASIC was damaged during safe-to-mate procedures, as it is indicated that high voltage was applied between pins, most likely pin5 (pin5 of U55 measured 100 Ohms to GND, and pin 6 measured 9kOhm to GND). It is also possible that the ASIC failed because it was not pre screened. ASIC, U55 was replaced and the TEM/TPS unit passed all performance testing.
       

Disposition Area

Defect Code:  050 Electronic/Electrical

Disposition:  Rework 
(Valid  dispositions:  Rework, Repair, Use-as-is, Reclassify, Return to Vendor, Scrap, or Documentation Change)

Disposition Instructions:  
The ASIC GTCC1 U55 was replaced. It is possible the ASIC was damaged during safe-to-mate procedures, as it is indicated that high voltage was applied between pins, most likely pin5 (pin5 of U55 measured 100 Ohms to GND, and pin 6 measured 9kOhm to GND).
It is also possible that the ASIC failed because it was not prescreened. After the ASIC GTCC1 U55 was replaced, the TEM/TPS unit was fully retested and passed all performance testing requirements per documents LAT-TD-03415 and LAT-TD-01652. The TEM/TPS unit will remain at SLAC temporarily before being shipped back to Italy.

NCR closure approved by David Nelson, LAT DAQ Engineering, and Y.C. Liew, LAT Quality Engineering (e-mails on file).

Root Cause: 
The most likely reason is the ASICs installed on the TEM boards were not prescreened. However, there was evidence that high voltage was applied between pins. This error was not present when the unit left SLAC. When tested upon return from Italy, the error was found by the software.

Action taken to Preclude Recurrence of Discrepancy: 
All flight ASICS are prescreened and passed 168 hours B/I at +85 degree C.
The customer should pay attention to safe-to-mate procedures as indication of high voltage was applied between pins.