I attached the results on TOT gain measurements. The first plot shows the TOT gain (us/fC) as a function of strip#. The second plot shows that as a function of FE#. In general, the TOT gain dispersion within a chip is larger than that between chips. (Sorry, I did not quantify it since it was obvious from those plots.) The rest of plot shows the TOT as a function of injected charge for selected strips. It is clearly observed that the slope is very different between strips.
The first two files are for the same layer with different splits (0/24 and 24/0). No obvious difference is seen. The last strips are for the X1=(6,7,0) where large discrepancy of TOT was observed between two GTRC. Since split was 4/20 in this layer, there was concern about the TOT discrepancy. From this measurements, it is clear that split does not affect TOT performance. X1 seems to be a special case where low-TOT FEs are happended to be in the first 4 FEs. (It appears that TOT gain is increasing with strip#. But I think this is nothing to do with the split since the first 4 FEs are readout from the low side GTRC and very close to it. If this trend is true, it could be something to do with power distribution although I doubt it.)
PS. I will need to correlate with TACK scan and gain measurement results.