GTRC-V6 Failure Review
and GTRC-V7 Design Review
Action Items from the Review |
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Item | Who | Status | |
1 | Resolve GTRC6 Mini-Tower test results (No TOT timeout with Van der Graaf). Estimate the rate of TOT overlap and compare with observed time-out rate. | Hiro Tajima | Hiro's note 11/27/03 |
2 | Test GTRC7 VHDL code in FPGA with a long TREQ (GTFE pulse) and many TACK. The length of the TREQ should be longer than the longest pulse you expect from heavy ions in the space. | Mutsumi Sugizaki | Mutsumi's note 12/1/03 |
3 | Improve handling of Test Vectors for GTRC6 & GTRC7:
Designer should propose test vectors used in testing. Designer should verify the % of coverage in VHDL |
Jeff Olsen (communicate to Mutsumi) | |
4 | Provide documentation of GTRC – describe the different states of the state machine. | Jeff Olsen | |
5 | Perform high rate triggering tests with single tray and radioactive source. | Luca Latronico | in progress |
6 | Continue system tests with multiple tray/multiple MCM using TEM, preferable with ELEX/DAQ group involvement. This should include a high-rate test of the mini-tower if possible. | Hiro Tajima |
In progress, but a high-rate test of the mini-tower with actual particles probably will never happen. |
7 | Continue to perform coordinated, but independent test with present mini-tower (at SLAC) and the new mini-tower (at INFN) | Hiro Tajima
Luca Latronico |
In progress with the mini-tower at SLAC. See Hiro's presentation at the Jan 21 all-hands meeting. |
8 | Test results vs. specifications: Provide a matrix comparing specifications described in LAT-SS-00152-02 and the test results. | Robert Johnson | |
9 | Produce new schedule for GTRC / MCM production and testing, taking in account downtime of foundry. | Robert Johnson
David Rich |
See the Jan 28 Tracker presentation. GTRC 7 wafers were received from MOSIS and a wafer tested by Jan 27. The wafer will be diced by Feb 3 and tested on MCMs that week. MCM production at Teledyne should start Feb 9. |
10 | Review requirements for normal / worst cases operations (temp, voltage, freq), together with ELEX group. | Robert Johnson | Based on tests of MCMs with the GTRC7 chip, we agreed upon a nominal voltage setting of 2.6V, at the TEM/PS, for AVDDB and DVDD. |
11 | Perform tests of interplay of Polyswitches and protection resistors. | Robert Johnson | Issue closed Jan 29, 04. See Marcus Ziegler's report (pdf) and the associated note. |
12 | For future ASIC programs at SLAC improve robustness of ASIC
development flow
- e.g., digital simulation instead of SPICE - test vector generation should be done from simulations |
Gunther Haller |
Owner: Robert Johnson
Last Modified: 02/06/2004 02:00 PM