2.  TECHNICAL SYSTEMS EVALUATIONS

 

2.1        Reviewers: Helmuth Spieler and Gary Sneiderman

 

2.1   Tracker (WBS 4.1.4)

 

Reviewers: Helmuth Spieler (Lawrence Berkeley National Laboratory) and Gary Sneiderman (Goddard Space Flight Center)

 

 

2.1.1   Findings (spell out cost and schedule)

2.1.1    

§       As noted in past reviews, this is a well thought out design that can be completed within the required time.

§       As noted in past reviews, this is a well thought out design that can be completed within the required time.

§       The bottoms-up cost estimate yields a total subsystem cost of  $9.9M with a contingency of 25%. Both are reasonable.

§       The design uses mature and well-tested technologies, so the technical risk is low, provided the procedures for design and verification developed by the Project are followed.

§       Issues Issues from last review:

o      Contingency:

§       Has been increased from 11% to 25%

o      Schedule float:

§       Schedule float is still marginal.The revised schedule shows increased float

o      Verification plans and test procedures:

§       Test plans and procedures are now at, or beyond, the level expected for PDR.

§       Substantial progress has been made in the mechanical design

o      Many of the assembly details have been completedworked out.

o      Mechanical tests have been performed and have provided valuable technical feedback for the design.

o       Mechanical tests have been performed and have provided valuable technical feedback for the design.

§       The Italian groups are fully integrated into the subsystem efforts and are making good progress.

§       The project schedule uses a US calendar that does not include Italian holidays. Currently this is being managed by manually changing task durations.

§       Both the digital and front-end integrated circuits that had been submitted at the time of the last review are dysfunctionalnot usable for full pre-production system tests. Nevertheless, partial tests were possible and have led to circuit improvements. Four new chips, two digital chips and two front-end chips, have been submitted for fabrication and are due back next month on August 21, 2002.

o      If these chips are acceptable as pre-production prototypes, the current schedule leaves sufficient time for system testing prior to commencement of full integrated circuit production on December 6, 2002.

o      If only minor modifications are necessary, a two-stage production schedule could preserve the planned production start with acceptable risk.delay appears to be unavoidable.

§       Two key electronic components are not flight qualified, high voltage chip capacitors and poly-switches. The capacitor vendor has assumed responsibility for flight qualification, however, the project must ensure that the poly-switches are acceptable for flight by January 2003.

§       A full analysis of the required number of spare components has not been completed.

 

 

 

 


2.1.1   Comments

 

As noted in past reviews, this is a well thought out design that can be completed within the required time. In the meantime, additional tests and analyses have been performed. Some of these have uncovered problems, but acceptable solutions have been found and are being implemented.

 

The January review raised several issues. Contingency was inadequate, but has now been increased from to 25%. This is an appropriate amount of contingency for this phase in the project. Schedule float was marginal. Increasing the overall duration of the project has allowed increased schedule float. However, as discussed below, there are several potential problems that could delay the schedule beyond the current limits. Preparation of verification plans and test procedures had begun, but additional effort was needed to put draft plans into place for upcoming tests. These test plans and procedures are now at, or beyond, the level expected for PDR.

 

Substantial progress has been made in the mechanical design. Many details of the mechanical design and assembly process have been developed. Mechanical tests have been performed and have provided valuable technical feedback for the design.

 

Several problems were identified through mechanical testing. Screw fasteners backed out during the first vibration test. Use of different screws allowed the full torque to be applied and appears to have solved the problem. This was verified in the second vibration test.

 

However, hairline cracks that had developed at the corners of the bottom tray in the first vibration test grew and additional cracks formed during the second vibration test.

 

The design of the bottom tray has been modified, which should resolve the strength problems. This modified design will be incorporated in the engineering model tower. A study team has been formed to perform analysis to identify other weak points and to recommend non-destructive testing methods for crack identification.

 

To address thermal concerns raised at the last review, the design of the Tracker Carbon Fiber Side Panels has been changed. This new design needs to be strength and thermally verified before committing to the production of the flight Side Panels.

 

The Tracker Trays and Towers will be fabricated, assembled, and tested in Italy. The Italian groups are fully integrated into the subsystem efforts and are making good progress. Technical and programmatic coordination between the US and Italian groups is crucial and is working well.

 

The project schedule uses a US calendar that does not include Italian holidays. Currently this is being managed by manually changing task durations. This could become difficult to manage as the schedule shifts. An international calendar should be incorporated into the project scheduling program to facilitate efficient tracking of international efforts.

 

Two key electronic components are not flight qualified, high voltage chip capacitors and polyswitches. The capacitor vendor has assumed responsibility for flight qualification, however, the project must ensure that the polyswitches are acceptable for flight by January 2003. The polyswitches can be replaced by jumpers without affecting the schedule, but this will reduce overall reliability. For example, without the polyswitch, a shorted capacitor could disable an entire tower.

 

[Mention existing chip design that was demonstrated on Balloon flight – good digital section, minor modification to analog section] Differences from Balloon flight chip – pitch is 30 microns larger, ladder is 35 cm long vs 32 cm, different protocol, different commands, clock now runs full-time, DC coupling to AC coupling. Add statement about what was learned from these chips.

 

Both the digital and front-end chips that had been submitted at the time of the last review are dysfunctional. Four new chips, two digital chips and two front-end chips, have been submitted and are due back next month. Two of the three previously submitted integrated circuits failed due to design verification flaws. The third chip failed because a “simple” modification was made and the chip circuit and layout were not verified prior to submission.

The electronics group has adopted additional extraction and verification tools to avoid future verification problems. The failure of the third chip indicates procedural problems that should be rectified in the future.

If the new chips are acceptable as pre-production prototypes, the current schedule provides adequate, although not ample, time to begin chip production on December 6, 2002. A full set of system tests must be completed to determine the adequacy of these designs. Should any changes be necessary, a new design must be prepared, verified, submitted, and tested before full production can begin. This would entail production delay of at least several months. In any case, test procedures and test hardware must be in place prior to the receipt of the chips from the current run to identify problems early.

 

The Key Milestones do not include the final integrated circuit production run submission. As has become apparent, this is a critical path milestone. Key milestones should be reviewed to ensure that critical path tasks are not omitted.

 

 

2.1.2   Recommendations

 

1)          Baseline the Tracker Subsystem.

 

21)          Ensure thorough and stringent testing, coupled with critical evaluation, of tower electronics at least to the multi-ladder level before releasing the designs for full production.

Prepare test systems for wafer level and system level tests expeditiously to allow full chip testing when front-end and digital chips arrive in August.

 

32)          Verify crack remediation and new side panel design (prior to the Engineering Model mechanical test.CDR).

 

43)          Compile data and conduct necessary tests to allow decision on poly-switches by the end of this year.

 

54)          Review schedule and milestones when full testing of the current round of integrated circuits has been completed to ensure adequate schedule contingency.

 

65)          Develop a spares plan by the time of CDR.