Helmuth Spieler

Hartmut Sadrozinski

Dick Horn


GLAST LAT Tracker ASIC Review


A review of the GLAST LAT TKR ASICs was held on 6-Dec-2002.

Charge:             Review the procurement readiness of the LAT TKR ASICs.

Reviewers:             T. Borden, D. Freytag, R. Horn, T. Kamae, D. Marsh, H. Sadrozinski,

H. Spieler, H. Tajima, N. Virmani

Background material is at



I. Findings


1. Front-End Analog ICs


Both the GTFE-G and GTFE-F2 are functional, but both show behavior that precludes a decision on the flight IC at this time. Several characteristics of these ICs merit further investigation, but at this point we concentrate on the major roadblocks to flight acceptance.


1.1. GTFE-F2


The threshold scan curves show a “ragged” behavior, which indicates some form of cross-talk. This phenomenon appears to be related to occupancy, as calibration scans triggering 8 channels simultaneously show better results than scans with 32 channels. The threshold dispersion also increases when more channels are scanned simultaneously. The last two channels of each IC are especially afflicted. In the experiment occupancies will be lower than in the threshold scans performed to date, so these results are not necessarily fatal for the experiment.


The noise levels derived from the threshold scans (~ 2000 e) are higher than simulated and also higher than measured on the GTFE-G (~1500 e). However, the data shown for noise rate vs. threshold show approximately the same noise performance for both ICs, so the higher noise may be an artifact of the threshold problem. Depending on the cross-talk mechanism, modifications to the MCM could improve performance, but that is not clear at this time.


The layout of the GTFE-F2 shows several areas where cross-talk could dynamically affect the comparator thresholds. A revised layout has been completed.


1.2. GTFE-G


The GTFE-G shows acceptable performance, except that roughly 20% of the ICs oscillate at unacceptably high threshold settings. Disabling the “threshold conditioner” appears to solve this problem, although the reason is not yet understood. A revised layout (“GTFE-G2”) is in hand which eliminates the “threshold conditioner”.



2. Digital Readout IC


The GTRC could not be tested at the wafer level, so yields are not available. However, they appear to be acceptable, from the number of working ICs, but this must be verified. GTRC ICs have been tested in “quite a few” mini-MCMs and in three full-sized MCMs. The major problem is the lack of timing margin. Margin can be recovered by increasing the supply voltage (and overall power dissipation) or reducing the clock frequency. The IC appears to function as designed, but since not all eventualities can be simulated, further system tests are needed to verify sufficient robustness for flight. The functions have been replicated in an FPGA to further analyze the problem. Proposed circuit changes have been implemented in the FPGA and verified. 



3. Ladders and Trays


Front-end ICs were tested using mini-MCMs connected to a full-length ladder. Two ladders are of high quality, whereas the third suffered from a relatively large number of defective detector strips, which is attributed to faulty coupling capacitors incurred during repetitive wire-bonding. In addition, ICs have been provided to Pisa for the fabrication of three complete trays with both sides populated and 2 trays with one side. These are expected in mid-January. This will allow extensive tests on a representative part of the full system.


4. Engineering Model (EM)


The EM will contain several live trays populated with the existing ASICs. Both GTFE-F2 and GTFE-G will be used, but on separate MCMs, as well as the existing GTRC. This will allow a thorough system test of the ASICs.


5. Action proposed by the TKR Manager


GTFE: Submit both the F2 (without change) and the G2 chips (with the threshold conditioner removed) such that a large enough number of either will be available for flight  production.

GTRC: Submit GTRC4 (unchanged) and GTRC5 (September 02 submission) and GTRC6 (FPGA tested) such that a large enough number of either will be available for flight  production.



II. Recommendations


The following recommendations seek to maintain the schedule while ensuring the quality required for launch. The rationale is to submit new wafer runs that could provide ICs for production. By submitting both GTFE-F2 without changes and GTFE-G with a “minor” change (GTFE-G2), one could obtain one design with acceptable performance. Since both ICs require further tests, the test program should continue unabated and expand to include the tray engineering models due in January. A decision on which IC to use for the flight hardware depends on many considerations, but it may have to await completion of the proposed fabrication run and complete testing of both ICs both on ladders and in the EM. The GTRC could be usable at a reduced clock rate or higher supply voltage, but this must be investigated further. Revised designs should be submitted in parallel with the analog ICs.


Specific recommendations (unless a chip version is specified, recommended measurements apply to all versions). GTRC related recommendations are grouped at the end.


1. Develop a plan to determine quantities of ICs required vs. time.


This would guide the procurement strategy: how many of each version to buy when, common mask of the different versions etc.


2. Submit wafer fabrication runs for GTFE-F2 (without changes) and GTFE-G2 (GTFE-G without the “threshold conditioner”).


     Rationale: The GTFE-F2 may be usable as is, if good threshold performance can be demonstrated at low occupancies, so this provides a “no change” option.  GTFE-G would be acceptable, except for uncertainties in the behavior of the “threshold conditioner”. Since no compelling case was made for the inclusion of this circuit element, it should be removed. As this is only an ancillary circuit element, the key functionality of the IC could be unaffected. However, this “minor modification” is a change and carries some risk.


3. Continue the measurement program at full scope and expand it to include the tray engineering models being assembled in Italy.


4. Investigate GTFE-F2 behavior at low occupancy.


     Perform threshold/calibration scans on only one channel at a time. Investigate deterioration as number of scanned channels increases.


5. Measure noise occupancy vs. threshold and determine at which threshold level the occupancy deviates from gaussian noise. This indicates at which threshold level spurious pickup becomes important. This measurement should be performed on individual modules and – as a final check – at the tray level.


     See www-physics.LBL.gov/~spieler for a more detailed discussion, for example in the ICFA lectures in Morelia (“Rate of Noise Pulses in a Threshold Discriminator System” in the Appendices; see p. 42 for an example)


6. Take threshold scans over full dynamic range to derive full calibration curve and check if the measured noise corrected for the gain is constant. At low thresholds determine at which level the noise deviates from the expected response to assess level of spurious signals (e.g. cross-talk). Do threshold scans in both direction.


7. Determine the acceptable noise rate per IC to determine margin for noise level and threshold variations. Determine the absolute scale of the gain and determine if the particle detection efficiency has the required margin if the threshold is increased.


8. In the GTFE-G, disable the “threshold conditioner” on some good ICs to see if there is any effect. Repair some more defective ICs and measure their performance.


9.  Test carefully TOT with respect to counting rate and heavy ion charge deposit.


10.  Submit for fabrication the revised GTRC (GTRC6). As a fall-back the existing GTRC could be included in the same reticle, possibly together with alternative new designs, depending on the perceived risk.


11. From systems considerations determine the minimum acceptable clock rate for the   GTRC and compare with the maximum rate that provides sufficient timing margin.


12. Test the GTRC and readout system at high random trigger rates.


13. Verify functionality of GTRC wafer test system prior to arrival of new ICs.


14.  Get sign-off on approved parts list


15.  Prepare required procurement docs.