The problems or features are in the GCFE design.  This is an explanation of the situation:

1.  The GCFE has a single VDD (3.3V) relative to ground.
2.  The shaping amplifiers are biased off of ground by about 125 mV to improve small signal linearity.
3.  Output amplifiers are included to get full scale amplitude correct but the circuitry to remove the 125 mV bias pedestal created both power and complexity issues according to the chip designers - Dieter Freytag and Gunther Haller.  The useful Range is about 125 mV to 2500 mV.

4.  The voltage reference for the ADCs is 2500 mV so that full scale out of the GCFE is full scale on the ADC.  However, since the ADC has circuitry to work from 0 mV, our 125 mV baseline (pedestal) results in the loss of the lowest 5% of the ADC.  There is no way to compensate for this without floating something (either ADC or GCFE) relative to ground.  This is not so much a loss of dynamic range but a translation  in ADC space.

5.  For the LEX8 and HEX8 ranges, this pedestal gets even worse because it is transferred thru switched capacator amplification circuit with varying leakage currents and switching characteristics that cause dramatic variation in LEX8 and HEX8 pedestal values from chip to chip.  LEX8/HEX8 pedestals vary in the range of 200 to 800 ADC tics (~ 100 to 400 mV).  The LEX1 and HEX1 pedestals are much better behaved around 200 ADC tics.

6.  The dynamic range for CAL is limited by noise on the low end and by overall system gain at the high end.   The original design was to get to 100 GeV in a single log.  Two things intervened after that - the CAL log got thinner (15%) and the light yield of the CDEs turned out to be 30 - 40% higher than expected.  By selecting the lowest commandable gain on the GCFE we get to around 70GeV.  Simulations show that this is mostly OK.

I believe that we want to be able to measure the full pedestal distribution - it's a good measure for tracking the noise.


W. Neil Johnson